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NXP Semiconductors /LPC43xx /SGPIO /CLR_EN_0

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Interpret as CLR_EN_0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLR_SCI0RESERVED

Description

Shift clock interrupt clear mask

Fields

CLR_SCI

1 = Shift clock interrupt clear mask of slice n.
RESERVED

Reserved.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data